The present invention relates generally to a programmable boundary scan and input/output parameter device for testing integrated circuits; and more particularly to a field programmable and configurable boundary scan integrated circuit with programmable input/output parameters.
Boundary scan is an emerging test standard which improves the testability of integrated circuits and their final subassembly apparatus such as a PC board or multi-chip module. The boundary scan concept is defined by the IEEE Std 1149.1-1990: IEEE Standard Test Access Port and Boundary-Scan Architecture, published by the Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, N.Y. 10017, U.S.A. As an aid to understanding the standard, see the book by Harry Bleeker, Peter van Den Eijnden and Frans de Jong titled Boundary-Scan Test, a Practical Approach, Kluwer Academic Publishers, 101 Philip Drive, Norwell Mass. 02061, U.S.A. The IEEE standard and the Bleeker et al. book are hereby incorporated by reference as background material, and for their detailed description of boundary scan circuits and test methods.
At present a small percentage of available integrated circuits offer boundary scan capability. Integrated circuit manufacturers are, in some cases, reluctant to add or include boundary scan in specific intergrated circuits due to added complexity, chip size, power dissipation, yield, the fact that many end users may not need boundary scan capability cost and other factors such as circuit performance degradation.
Present manufacturers of printed circuit boards, multi-chip modules, and other electronic digital assemblies also have difficulty in implementing boundary scan testing as required by their application, since many integrated circuits do not provide boundary scan implementation. Many new integrated circuits do not have boundary scan, and manufacturers are reluctant to redesign existing circuits.
The following United States patents are of interest with respect to the present invention.
U.S. Pat. No. 5,198,778--Akabane PA1 U.S. Pat. No. 5,187,430--Marek et al PA1 U.S. Pat. No. 5,148,102--Rose et al PA1 U.S. Pat. No. 4,967,148--Doemens et al PA1 U.S. Pat. No. 5,281,864--Hahn et al PA1 U.S. Pat. No. 5,155,732--Jarwala et al PA1 U.S. Pat. No. 5,042,034--Correale Jr. et al PA1 U.S. Pat. No. 5,276,586--Hatsuda et al PA1 U.S. Pat. No. 5,247,423--Lin et al PA1 U.S. Pat. No. 5,241,450--Berhardt et al PA1 U.S. Pat. No. 5,208,729--Cipolla et al PA1 U.S. Pat. No. 5,200,580--Sienski et al PA1 U.S. Pat. No. 5,167,512--Walkup PA1 U.S. Pat. No. 5,137,836--Lam PA1 U.S. Pat. No. 4,930,002--Takenka et al
The patent to Marek et al discloses a method for determining networks among nodes in a circuit board by applying an electrical stimulus, measuring the response at the nodes, and comparing the measurements to determine a plurality of networks among the nodes. The remaining patents are of less interest.
The following United States patents relate to boundary-scan testing, and are hereby incorporated by reference.
The following United States patents relate to Multi Chip Module (MCM) technology, and are hereby incorporated by reference to show the chip assembly and wire bonding techniques.